In conventional integrated circuit fabrication processes an integrated circuit layout design is generated that includes multiple layers of design data. The integrated circuit layout design is then sent to a photomask vendor who generates photomasks that are to be used in the subsequent fabrication process. More particularly, each layer of design data is converted into a single photomask that includes multiple die regions that include the design features indicated by the layout design. Portions of the photomask that are outside of the die regions, typically referred to as “blading areas,” extend on all four sides of each photomask. These blading areas are typically left blank and are covered during the exposure process by blades.
During the integrated circuit manufacturing process semiconductor wafers are subjected to numerous process steps, with each process step performed sequentially on a particular semiconductor wafer. Conventionally, for each process step that requires patterning, a single photomask is used to transfer the pattern to individual semiconductor wafers.
With technologies moving to ever smaller feature sizes, integrated circuit designs and manufacturing processes have become increasingly complex. As a result there has been a growing need to test integrated circuit designs and manufacturing processes. Conventionally, test patterns are taped out to scribe lines located between die regions. However, scribe lines are long and thin, limiting the number of test patterns that can be formed on each photomask. Moreover, it is impractical to purchase additional photomasks for testing because of the high cost of photomasks. Accordingly, there is a need for a method for forming test structures on semiconductor substrates that does not require taping out test structures to scribe lines. Moreover, there is a need for a method for forming test structures on semiconductor substrates that does not increase the number of photomasks. The present invention meets the above needs.